A dual-port fastbus memory to test the L3 data acquisition system

Journal Article · Fri Apr 01 04:00:00 EST 1988 · IEEE Trans. Nucl. Sci.; (United States)

DOI:https://doi.org/10.1109/23.3691· OSTI ID:7019755

Cristofori, P P; Cesaroni, F; Falciano, S; Medici, G

The authors describe a dual-port 0.25 Mbytes (64 KI . 32 bits) FASTBUS Memory module which implements a large set of functions on the Crate Port, while the Cable Port is mainly used for Data transfers. Linear and Circular FIFO-like modes are software- selectable. Two pointers are available for write and read operations respectively. The Memory, successfully used to test the L3 Event Builders, exhibits features of an interesting, general purpose, FASTBUS module for event buffering in large Data Acquisition Systems.

• Research Organization: Universita degli Studi 'La Sapienza' and I N F N, Roma (IT)
• OSTI ID: 7019755
• Journal Information: IEEE Trans. Nucl. Sci.; (United States), Journal Name: IEEE Trans. Nucl. Sci.; (United States) Vol. 35:2; ISSN IETNA
• Country of Publication: United States
• Language: English

Related Subjects

99 GENERAL AND MISCELLANEOUS
990220* -- Computers
Computerized Models
& Computer Programs-- (1987-1989)
COMMUNICATIONS
DATA ACQUISITION SYSTEMS
DATA TRANSMISSION
MEMORY DEVICES