Robot control computation in microprocessor system with multiple arithmetic processors using a modified DF/IHS scheduling algorithm
- School of Electrical Engineering, Purdue Univ., West Lafayette, IN (US)
- Luoying Institute of Tracking and Telecommunications Technology, Henan (CN)
The problem of designing a high performance robot controller with multiple arithmetic processing units (APU's) is addressed. One attractive feature about this controller is that a minimum number of special purpose hardware components are needed, and in fact off-the-shelf components can be used. In the controller described, one main processor (MPU) schedules a number of APU's to produce the computational throughput. In this design an efficient scheduling algorithm plays the most important role in the system performance. The depth first/initial heuristic search (DF/IHS) algorithm is an efficient algorithm that solves difficult nonpolynominal (NP)-complete problems of scheduling a set of particularly ordered computational tasks onto a multiprocessor system. When interprocessor communication overheads are appreciable, it is not very effective in providing a practical near-optimum schedule. It fails to consider the problem of contention for shared resources. A new multiprocessor scheduling algorithm, which minimizes the effects of overhead and by doing so it reduces the effect of contention, is presented. This scheduling algorithm is used to derive the operational instructions of the APU's and the MPU for one multiple APU-based robot controller.
- OSTI ID:
- 6992111
- Journal Information:
- IEEE Transactions on Systems, Man, and Cybernetics (Institute of Electrical and Electronics Engineers); (USA), Journal Name: IEEE Transactions on Systems, Man, and Cybernetics (Institute of Electrical and Electronics Engineers); (USA) Vol. 19:5; ISSN 0018-9472; ISSN ISYMA
- Country of Publication:
- United States
- Language:
- English
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