A new parallel sorting approach with sorting memory module
Journal Article
·
· Journal of Parallel and Distributed Computing; (USA)
- Illinois Univ., Urbana, IL (USA). Center for Supercomputing Research and Development
- Research and Development, Concurrent Computer Corp., Tinton Falls, NJ (US)
- Dept. of Computing Science, Univ. of Alberta, Edmonton, Alberta (CA)
A new approach to accelerating parallel sorting processes is introduced in this paper. This approach involves the design of a new type of memory chip with sorting functions. This type of sorting memory chip is feasible with today's VLSI techniques. A memory module organizing several sorting memory chips associated with additional ECL or TTL control logic circuits is also presented. Using the sorting memory modules in a shared memory parallel processor machine, parallel sorting algorithms such as the column sort method can reduce the row access time significantly and avoid data collisions in the interconnection network. Experimental simulation results on the practical speedup achieved and the memory utilization for the proposed approach are described.
- OSTI ID:
- 6960981
- Journal Information:
- Journal of Parallel and Distributed Computing; (USA), Journal Name: Journal of Parallel and Distributed Computing; (USA) Vol. 7:3; ISSN JPDCE; ISSN 0743-7315
- Country of Publication:
- United States
- Language:
- English
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