Skip to main content
U.S. Department of Energy
Office of Scientific and Technical Information

The Fastbus Intersegment Processor (FIP)

Conference · · IEEE Trans. Nucl. Sci.; (United States)
OSTI ID:6944530
The Fastbus Intersegment Processor (FIP) is a Fastbus processor based on a MOTOROLA MC68020 microprocessor system. It will be used in several detectors of the Delphi LEP experiment at CERN. Its architecture is oriented towards cellular multi-layered acquisition systems, where it provides data collection, processing and buffering at a particular level, as well as control and synchronisation from one level to the next. The Fastbus architecture, Fastbus interfaces, and the application foreseen for the Delphi TPC are covered in detail in the paper.
Research Organization:
CEN Saclay, 91191 Gif-Sur-Yvette Cedex
OSTI ID:
6944530
Report Number(s):
CONF-861007-
Conference Information:
Journal Name: IEEE Trans. Nucl. Sci.; (United States) Journal Volume: NS-34:1
Country of Publication:
United States
Language:
English