Voltage-clearance recommendations for printed boards
Present and future trends in printed board designs point to higher circuit densities with narrower lines and closer spacings. Some designers are now laying out boards with 0.13 mm lines and spacings. The reduction of nominal spacing between conductive elements has raised questions concerning the adequacy of present voltage-clearance recommendations. The present recommendations are considered too conservative in that they are weighted with large safety factors, especially for small clearances, and are frequently disregarded by many designers. Published voltage breakdown measurements made on printed boards with comb patterns with their enhanced conductor test lengths show breakdowns occurring at much higher voltages than those specified for the clearances in existing documents. A Task Group was set up to review published breakdown measurements and to make any additional measurements necessary to provide voltage-clearance recommendations. These recommendations are reported.
- Research Organization:
- Sandia National Labs., Albuquerque, NM (USA); Delsen Testing Labs., Glendale, CA (USA); Rockwell International Corp., Cedar Rapids, IA (USA); Bell Labs., Richmond, VA (USA); Trace Labs., Canoga Park, CA (USA); Naval Avionics Facility, Indianapolis, IN (USA); Square D Co., Milwaukee, WI (USA)
- Sponsoring Organization:
- USDOE
- DOE Contract Number:
- AC04-76DP00789
- OSTI ID:
- 6872407
- Report Number(s):
- SAND-80-2065C; CONF-800991-1
- Resource Relation:
- Conference: Fall 1980 IPC meeting, Chicago, IL, USA, 28 Sep 1980
- Country of Publication:
- United States
- Language:
- English
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