Performance analysis of a parallel logic simulation machine

Journal Article · Thu Nov 30 23:00:00 EST 1989 · Journal of Parallel and Distributed Computing; (USA)

DOI:https://doi.org/10.1016/0743-7315(89)90029-4· OSTI ID:6845625

Wong, K; Franklin, M A ^[1]

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1. Computer and Communications Research Center, Washington Univ., St. Louis, MO (US)

The high costs associated with logic simulation of large VLSI circuits has led to the need for new computer architectures tailored to the simulation task. Such architectures have the potential for significant speedups over software-based logic simulators executing on standard sequential computers. This paper presents a model of one class of multiprocessor simulation architectures and compares the performance of some of these machines using data obtained from simulations of VLSI circuits. In addition, the authors discuss the implications of our results on machine design.

• OSTI ID: 6845625
• Journal Information: Journal of Parallel and Distributed Computing; (USA), Journal Name: Journal of Parallel and Distributed Computing; (USA) Vol. 7:3; ISSN JPDCE; ISSN 0743-7315
• Country of Publication: United States
• Language: English

Related Subjects

42 ENGINEERING
426000 -- Engineering-- Components
Electron Devices & Circuits-- (1990-)
99 GENERAL AND MISCELLANEOUS
990200* -- Mathematics & Computers
ARRAY PROCESSORS
COMPUTER ARCHITECTURE
COMPUTERIZED SIMULATION
DESIGN
ELECTRONIC CIRCUITS
INTEGRATED CIRCUITS
LOGIC CIRCUITS
MICROELECTRONIC CIRCUITS
PARALLEL PROCESSING
PERFORMANCE TESTING
PROGRAMMING
SIMULATION
TESTING