Combinational circuit design verification using SETS
A technique is presented for automatically verifying the correctness of combinational circuit designs without the use of simulation. Design verification is accomplished by use of SETS (Set Equation Transformation System)--a computer program for symbolically manipulating Boolean equations. The initial specification and the final circuit realization are regarded as independent logical structures that define sets of Boolean output variables in terms of a specified set of input variables. The function defined by the circuit is equivalent to the function defined by the input specifications if and only if the exclusive-OR of the two functions is identically zero. If these functions are equivalent, the circuit realization has been proven to be correct. If they differ, the circuit design is faulty.
- Research Organization:
- Sandia Labs., Albuquerque, NM (USA)
- DOE Contract Number:
- EY-76-C-04-0789
- OSTI ID:
- 6806841
- Report Number(s):
- SAND-78-1933
- Country of Publication:
- United States
- Language:
- English
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