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U.S. Department of Energy
Office of Scientific and Technical Information

Concurrent computer architecture

Technical Report ·
OSTI ID:6788669
Present-generation concurrent computers offer performance greater than vector supercomputers and are easily programmed by nonexperts. Evolution of VLSI technology and a better understanding of concurrent machine organization have led to substantial improvements in the performance of numerical processors, symbolic processors, and communication networks. A 100MFLOPS arithmetic chip and a 5-us latency communication network are under construction. Low-latency communication and task switching simplify concurrent programming by removing considerations of grain size and locality. A message-passing concurrent computer with a global virtual address space provides programmers with both a shared memory, and message-based communication and synchronization. This paper describes recent advances in concurrent computer architecture, drawing on examples from the J-Machine and an experimental concurrent computer under development at MIT.
Research Organization:
Massachusetts Inst. of Tech., Cambridge (USA). Artificial Intelligence Lab.
OSTI ID:
6788669
Report Number(s):
AD-A-194566/6/XAB; VLSI-MEMO-87-422
Country of Publication:
United States
Language:
English