Performance of symbolic applications on a parallel architecture

Journal Article · Mon Jun 01 00:00:00 EDT 1987 · Int. J. Parallel Program.; (United States)

DOI:https://doi.org/10.1007/BF01407933· OSTI ID:6728216

Guzman, A; Krall, E J; McGehearty, P F; Bagherzadeh, N

The results of a study of a family of parallel symbolic architectures executing several parallel applications are presented. The class of architectures being simulated is characterized by a shared memory structure, by a hierarchical interconnect, and by clustered processors. Speedup measurements were obtained from six different application kernels. Measurements were also performed to assess the degradation of speedup as a function of the interconnection delays, and to study the effect of different scheduling algorithms. The results presented support the claim that the proposed architecture would be a powerful parallel symbolic computation system. The paper discusses processor starvation, fine grain parallelism, uneven loads, foreign reference, schedule and indeterminate computation with respect to the applications chosen.

• Research Organization: Micro-electronics and Technology Computer Corp., Austin, TX (USA)
• OSTI ID: 6728216
• Journal Information: Int. J. Parallel Program.; (United States), Vol. 16:3
• Country of Publication: United States
• Language: English

Related Subjects

99 GENERAL AND MISCELLANEOUS//MATHEMATICS, COMPUTING, AND INFORMATION SCIENCE
ARRAY PROCESSORS
COMPUTER ARCHITECTURE
PARALLEL PROCESSING
PERFORMANCE
TASK SCHEDULING
COMPUTER CALCULATIONS
COMPUTER CODES
COMPUTERIZED SIMULATION
DATA TRANSMISSION
EFFICIENCY
IMPLEMENTATION
KERNELS
COMMUNICATIONS
DATA PROCESSING
PROCESSING
PROGRAMMING
SIMULATION
990210* - Supercomputers- (1987-1989)