Logic simulation on a multiprocessor. Master's thesis

Technical Report · Sat Nov 01 04:00:00 EST 1986

OSTI ID:6636234

Bradley, E

The performance of circuit simulators running on SISD computers is fundamentally limited by the Von Neumann bottleneck. Multiprocessors do not share this limitation. The task of solving the equations for the many parallel signal paths found in most circuits lends itself readily to concurrent computation. For both of these reasons, parallel processing is a highly promising approach to circuit simulation. This thesis explores several facets of this problem. The logic simulator CONSIM was implemented in the parallel language Multilisp, which contains special constructs for dispatching tasks in parallel. A model for the simulator's behavior was developed using a series of experiments. The analysis explains the effects upon CONSUM's performance of several parameters, including: the number of nodes in the multiprocessor, circuit size and topology, and the algorithms for generating the simulation code and for taking advantage of its inherent parallelism. The final generation of these algorithms exposed and exploited significant parallelism, but did not attain linear speedup.

• Research Organization: Massachusetts Inst. of Tech., Cambridge (USA). Lab. for Computer Science
• OSTI ID: 6636234
• Report Number(s): AD-A-175776/4/XAB; MIT/LCS-380
• Country of Publication: United States
• Language: English

Related Subjects

99 GENERAL AND MISCELLANEOUS
990210* -- Supercomputers-- (1987-1989)
ALGORITHMS
ANALOG SYSTEMS
ARRAY PROCESSORS
ELECTRONIC CIRCUITS
FUNCTIONAL MODELS
LOGIC CIRCUITS
MATHEMATICAL LOGIC
MATHEMATICS
PARALLEL PROCESSING
PROGRAMMING
PROGRAMMING LANGUAGES
SIMULATORS
TOPOLOGY