Wireability of an Ultracomputer
Technical Report
·
OSTI ID:6628940
We analyze the wireability of an Ultracomputer, a shared-memory MIMD parallel machine with thousands of processing elements, wired using an Omega connection network. We show a way of structuring hardware involving large numbers of processors into smaller subsets of processors and switches. A design with 4096 processors, based on present-day wiring technology and electrical power considerations, is presented. This design assumes a 2 x 2 switch on a chip is available, also a 1 megabit memory chip and a high speed microprocessor chip with 32 bit addressing.
- Research Organization:
- New York Univ., NY (USA). Courant Mathematics and Computing Lab.
- DOE Contract Number:
- AC02-76ER03077
- OSTI ID:
- 6628940
- Report Number(s):
- DOE/ER/03077-177; ON: DE83004269
- Country of Publication:
- United States
- Language:
- English
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