Analysis, computer simulation, and properties of semiconductor dynamic memories for VLSI implementation

Thesis/Dissertation · Wed Jan 01 04:00:00 EST 1986

OSTI ID:6624887

Jeung, Y C

As overall dynamic random-access memory capacity and performance continue to increase and improve innovation is keeping pace to make basic cells smaller, faster, more reliable, and simpler. Two novel bipolar dynamic random-access memory (B-dRAM) cells are proposed, investigated, and analyzed. One cell incorporates three diodes in a composite structure and the other employees an npn transistor and a diode. Each of the basic cells consists of the junction capacitor, where data is stored in the form of charge, and the switching devices acting as a transfer gate. An open bit line organized array of cells is proposed with a simple sense/latch scheme and a dummy cell employed as a reference potential. This array organization can double the basic cells per sense/latch circuit as compared with a single-ended sense scheme. For the completeness of this thesis, the development of metal-oxide semiconductor field effect transistor (MOSFET) and of bipolar dynamic random-access memories are reviewed with emphasis on the memory basic cell structures in terms of cross-sectional and equivalent circuit view points, and including the sense/latch amplifier. A projected trend in the scalability of future dRAM's is discussed based on the available data. Finally some candidates proposed for memory cells of future dRAM's are discussed.

• Research Organization: Rhode Island Univ., Kingston (USA)
• OSTI ID: 6624887
• Country of Publication: United States
• Language: English

Related Subjects

99 GENERAL AND MISCELLANEOUS
990210* -- Supercomputers-- (1987-1989)
COMPUTERIZED SIMULATION
ELECTRONIC CIRCUITS
FIELD EFFECT TRANSISTORS
INTEGRATED CIRCUITS
MEMORY DEVICES
MICROELECTRONIC CIRCUITS
MOS TRANSISTORS
MOSFET
RANDOMNESS
SEMICONDUCTOR DEVICES
SIMULATION
TRANSISTORS