Efficient direct-method parallel circuit simulation using multilevel node tearing
The direct-method circuit simulation technique solves the entire system at every iteration and thus avoids the problem of slow convergence or even nonconvergence, which could occur when relaxation-based techniques are applied. However, the parallelism of the direct method is not as obvious as that of the relaxation technique. The parallelism in the LU factorization without tearing has been found to be small and one level node tearing could have a large border size if it is forced to partition the circuit into a fixed number of subcircuits. In this thesis we increase the parallelism by using a multilevel node tearing method which maintains a minimum border size while trying to balance the subcircuit sizes. The problems of how to maximize the speedup by scheduling the subcircuits correctly and by choosing the optimal number of levels of partitioning are also studied. A parallel circuit simulator, iPRIDE, is implemented on an ALLIANT FX/8 computer using these techniques. A speedup of 7.3 using 8 processors has been achieved.
- Research Organization:
- Illinois Univ., Urbana, IL (USA)
- OSTI ID:
- 6596776
- Country of Publication:
- United States
- Language:
- English
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Related Subjects
990200* -- Mathematics & Computers
990300 -- Information Handling
COMPUTER ARCHITECTURE
COMPUTERIZED SIMULATION
DATA PROCESSING
ELECTRONIC CIRCUITS
FUNCTIONS
INFORMATION SYSTEMS
LOGIC CIRCUITS
MULTILEVEL ANALYSIS
OPTIMIZATION
PARALLEL PROCESSING
PARTITION FUNCTIONS
PROCESSING
PROGRAMMING
SIMULATION
TASK SCHEDULING