IC chip stress during plastic package molding
Approximately 95% of the world`s integrated chips are packaged using a hot, high pressure transfer molding process. The stress created by the flow of silica powder loaded epoxy can displace the fine bonding wires and can even distort the metalization patterns under the protective chip passivation layer. In this study the authors developed a technique to measure the mechanical stress over the surface of an integrated circuit during the molding process. A CMOS test chip with 25 diffused resistor stress sensors was applied to a commercial lead frame. Both compression and shear stresses were measured at all 25 locations on the surface of the chip every 50 milliseconds during molding. These measurements have a fine time and stress resolution which should allow comparison with computer simulation of the molding process, thus allowing optimization of both the manufacturing process and mold geometry.
- Research Organization:
- Sandia National Labs., Albuquerque, NM (United States)
- Sponsoring Organization:
- USDOE, Washington, DC (United States)
- DOE Contract Number:
- AC04-94AL85000
- OSTI ID:
- 654171
- Report Number(s):
- SAND--98-0383C; CONF-980550--; ON: DE98002897; BR: DP0102022
- Country of Publication:
- United States
- Language:
- English
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