On mapping systolic algorithms onto the hypercube

Journal Article · Mon Jan 01 04:00:00 EST 1990 · IEEE Transactions on Parallel and Distributed Systems; (USA)

DOI:https://doi.org/10.1109/71.80124· OSTI ID:6541103

Ibarra, O H; Sohn, S M ^[1]

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1. Dept. of Computer Science, Univ. of Minnesota, Minneapolis, MN (US)

Much effort has been devoted toward developing efficient algorithms for systolic arrays. Here the authors consider the problem of mapping these algorithms into efficient algorithms for a fixed-size hypercube architecture. They describe in detail several optimal implementations of algorithms given for one-way one and two-dimensional systolic arrays. Since interprocessor communication is many times slower than local computation in parallel computers built to date, the problem of efficient communication is specifically addressed for these mappings. In order to experimentally validate the technique, five systolic algorithms were mapped in various ways onto a 64-node NCUBE/7 MMD hypercube machine. The algorithms are for the following problems: the shuffle scheduling problem, finite impulse response filtering, linear context-free language recognition, matrix multiplication, and computing the Boolean transitive closure. Experimental evidence indicates that good performance is obtained for the mappings.

• OSTI ID: 6541103
• Journal Information: IEEE Transactions on Parallel and Distributed Systems; (USA), Journal Name: IEEE Transactions on Parallel and Distributed Systems; (USA) Vol. 1:1; ISSN ITDSE; ISSN 1045-9219
• Country of Publication: United States
• Language: English

Related Subjects

99 GENERAL AND MISCELLANEOUS
990200* -- Mathematics & Computers
ALGORITHMS
COMPUTER ARCHITECTURE
COMPUTERS
HYPERCUBE COMPUTERS
MATHEMATICAL LOGIC
OPTIMIZATION
PARALLEL PROCESSING
PERFORMANCE
PROGRAMMING
TECHNOLOGY UTILIZATION