A multiple fault-tolerant processor network architecture for pipeline computing
Journal Article
·
· IEEE Trans. Comput.; (United States)
- Computer Center, Technical Univ. of Poznan, 60-965 Poznan (PL)
Certain fault-tolerant multiprocessor networks that can emulate linear array interconnections are considered. The system is fault tolerant of (m - 1) node and link failures. One of the particularly attractive features of this network is that it allows for a linear array structure starting with any node even in spite of (m - 2) faults. The configuration algorithm is fully distributed, and is performed on the basis of test results obtained from nonfaulty processors only. A simple fault identification procedure is developed using the above routing algorithm.
- OSTI ID:
- 6476452
- Journal Information:
- IEEE Trans. Comput.; (United States), Journal Name: IEEE Trans. Comput.; (United States) Vol. 37:11; ISSN ITCOB
- Country of Publication:
- United States
- Language:
- English
Similar Records
On an optimally fault-tolerant multiprocessor network architecture
Designing and reconfiguring fault-tolerant multiprocessor systems
A class of fault-tolerant multiprocessor networks
Journal Article
·
Fri May 01 00:00:00 EDT 1987
· IEEE Trans. Comput.; (United States)
·
OSTI ID:6595400
Designing and reconfiguring fault-tolerant multiprocessor systems
Thesis/Dissertation
·
Sun Dec 31 23:00:00 EST 1989
·
OSTI ID:7046530
A class of fault-tolerant multiprocessor networks
Journal Article
·
Fri Mar 31 23:00:00 EST 1989
· IEEE (Institute of Electrical and Electronics Engineers) Transactions on Reliability; (USA)
·
OSTI ID:5242595