Single event upset hardening techniques
Integrated circuit logic states are maintained by virtue of specific transistor combinations being either on'' (conducting) or off'' (nonconducting). High energy ion strikes on the microcircuit generate photocurrents whose primary detrimental effect is to make off'' transistors appear on,'' confusing the logic state and leading to single event upset (SEU). Protection against these soft errors is accomplished using either technology or circuit techniques, actions that generally impact yield and performance relative to unhardened circuits. We describe, and using circuit simulations analyze, a technique for hardening latches which requires combinations of technology and circuit modifications, but which provides SEU immunity without loss of speed. Specifically, a single logic state is hardened against SEU using technology methods and the information concerning valid states is then used to simplify hardened circuit design. The technique emphasizes some basic hardening concepts, ideas for which will be reviewed. 3 refs., 2 figs.
- Research Organization:
- Sandia National Labs., Albuquerque, NM (USA)
- Sponsoring Organization:
- DOE/DP
- DOE Contract Number:
- AC04-76DP00789
- OSTI ID:
- 6427281
- Report Number(s):
- SAND-90-1725C; CONF-901101-43; ON: DE91002337
- Resource Relation:
- Conference: American Nuclear Society winter meeting, Washington, DC (USA), 11-15 Nov 1990
- Country of Publication:
- United States
- Language:
- English
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Related Subjects
46 INSTRUMENTATION RELATED TO NUCLEAR SCIENCE AND TECHNOLOGY
MICROELECTRONICS
RADIATION HARDENING
ELECTRICAL TRANSIENTS
IONIZING RADIATIONS
LOGIC CIRCUITS
PHOTOCURRENTS
TRANSISTORS
CURRENTS
ELECTRIC CURRENTS
ELECTRONIC CIRCUITS
HARDENING
PHYSICAL RADIATION EFFECTS
RADIATION EFFECTS
RADIATIONS
SEMICONDUCTOR DEVICES
TRANSIENTS
VOLTAGE DROP
426000* - Engineering- Components
Electron Devices & Circuits- (1990-)
440200 - Radiation Effects on Instrument Components
Instruments
or Electronic Systems