The on-chip parallelism of VLSI circuits
Simulation is a bottleneck in VLSI circuit design. Not only are there many simulation runs throughout the design cycle, but each run can take hours or days to complete. One often suggested means of speeding up event-driven simulation is to use multiple processors to exploit the natural parallelism present in the circuit, that is to partition the circuit among multiple processors, with each executing the same algorithm on its portion of the circuit. This approach assumes that there is sufficient activity, or circuit parallelism, in the circuit to keep all of the processors busy. The author has used two approaches in this work. First, he has formulated a model for studying circuit parallelism and the potential speedup of parallel logic-level simulation. Using this model he has considered the effect of the choice of timing model and synchronization strategy on speedup. He has also investigated the effect of circuit size on parallelism. Additionally, he has developed a methodology for measuring circuit parallelism, and used it to determine the parallelism of nine circuits using two different simulators. Empirical measurements have also been used to validate portions of the formal model. The major results of the model are: (1) Unit-delay timing provides at least as much parallelism as variable-delay or fixed delay timing. (2) Asynchronous timing strategies can improve simulation speed over synchronous strategies. However, for unit-delay timing, if all event evaluation times are equal, the asynchronous strategies do not provide additional speedup over synchronous simulation. (3) In general, the percentage of parallelism is not constant over circuit size, even for members of the same circuit family.
- Research Organization:
- Washington Univ., Seattle, WA (USA)
- OSTI ID:
- 6309687
- Country of Publication:
- United States
- Language:
- English
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Related Subjects
990200* -- Mathematics & Computers
ALGORITHMS
ARRAY PROCESSORS
COMPUTER NETWORKS
COMPUTERIZED SIMULATION
DATA PROCESSING
DESIGN
DISTRIBUTED DATA PROCESSING
ELECTRONIC CIRCUITS
LOGIC CIRCUITS
MATHEMATICAL LOGIC
MEMORY DEVICES
PARALLEL PROCESSING
PROCESSING
PROGRAMMING
SEMICONDUCTOR DEVICES
SEMICONDUCTOR STORAGE DEVICES
SIMULATION