Hardware task scheduling mechanism for a real-time multi-microprocessor architecture
Efficient task scheduling and resource allocation schemes which take advantage of concurrent operations are crucial to the use of multiple microprocessor architectures in real-time applications. Since the data processing overhead associated with algorithmic scheduling mechanisms increases as the number of processors and tasks within the system increases, these scheduling mechanisms could prove to be the limiting factor on a machine's real-time performance capabilities. This paper presents the design of a hardware task scheduler, which by the efficient routing of control tokens, is able to map a problem space onto a distributed architecture. A possible single-chip implementation of the task scheduler and a discussion of the scheduler's expected performance is also presented. 7 references.
- OSTI ID:
- 6281987
- Country of Publication:
- United States
- Language:
- English
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