A fault-tolerant mapping scheme for a configurable multiprocessor system
This paper presents a fault-tolerant mapping scheme for a configurable multiprocessor system using multistage interconnection networks. By adapting its interprocessor connections, the multiprocessor system can provide many regular topological configurations suitable for a variety of parallel computation applications. The configurability of the system is achieved by applying a set of configuration procedures to a linear address space of the system. The central idea behind the proposed scheme is to use two transformations to restore such a linear address space in the presence of processor failures. The fault-tolerant mapping scheme is composed of three algorithms: Algorithm Single, Algorithm Double, and Algorithm Triple. The algorithms adaptively use the two transformations to handle three different types of faults: single fault, double fault, and triple fault or more. It is shown that in case of few processor failures, the algorithms can effectively achieve fault-free linear subspaces with graceful degradation.
- Research Organization:
- Computer Engineering Program, Dept. of Electrical Engineering, Pennsylvania State Univ., University Park, PA (US); Dept. of Electrical and Computer Engineering, the Univ. of Texas at Austin, Austin, TX (US)
- OSTI ID:
- 6275763
- Journal Information:
- IEEE Trans. Comput.; (United States), Journal Name: IEEE Trans. Comput.; (United States) Vol. 38:2; ISSN ITCOB
- Country of Publication:
- United States
- Language:
- English
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