A new class of rearrangeable interconnection networks
Thesis/Dissertation
·
OSTI ID:6223673
With the current interest in general purpose multiprocessing systems and distributed processing networks, a need exists for rearrangeable interconnection networks. These networks can simultaneously transmit information from all sources to all destinations, for all possible combinations of destinations. Such networks exist, and among these the Benes network is of asymptotically optimal hardware complexity. However, this network requires excessive time to recompute the switch settings each time a new set of transmissions is requested by the source processors. Some algorithms exist to reduce this time overhead but they require excessive hardware to compute the settings. This thesis introduces a new class of rearrangeable networks, called reduced networks, based on an extension of Clos three-stage networks. It is shown that the switches in the first and third stages of Clos networks can be constructed as unique path logarithmic networks. Only the center-stage switches must be rearrangeable. This fact is then used to develop a compact network structure. The routing properties of this structure are defined, and it is shown that there is a connectivity in the setting of the switches for any Clos network. An upper and lower bound on this connectivity are established, leading to a fast routing algorithm, with a trade off between the routing time and the network hardware complexity. This can be exploited by the network designer to achieve the best combination of hardware cost and data transfer rate for the particular application. For network sizes contemplated within the foreseeable future, the resulting design will in most cases be closer to the ideal combination than any other network.
- Research Organization:
- Rensselaer Polytechnic Inst., Troy, NY (USA)
- OSTI ID:
- 6223673
- Country of Publication:
- United States
- Language:
- English
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