Relaxation oscillation logic in Josephson junction circuits
A dc powered, self-resetting Josephson junction logic circuit relying on relaxation oscillations is described. A pair of Josephson junction gates are connected in series, a first shunt is connected in parallel with one of the gates, and a second shunt is connected in parallel with the series combination of gates. The resistance of the shunts and the dc bias current bias the gates so that they are capable of undergoing relaxation oscillations. The first shunt forms an output line whereas the second shunt forms a control loop. The bias current is applied to the gates so that, in the quiescent state, the gate in parallel with the second shunt is at V O, and the other gate is undergoing relaxation oscillations. By controlling the state of the first gate with the current in the output loop of another identical circuit, the invert function is performed.
- Assignee:
- Bell Telephone Laboratories Inc
- Patent Number(s):
- US 4249094
- OSTI ID:
- 6204807
- Country of Publication:
- United States
- Language:
- English
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Related Subjects
71 CLASSICAL AND QUANTUM MECHANICS
GENERAL PHYSICS
DESIGN
ELECTRIC CONDUCTIVITY
ELECTRICAL PROPERTIES
ELECTRONIC CIRCUITS
JOSEPHSON JUNCTIONS
JUNCTIONS
LOGIC CIRCUITS
OSCILLATIONS
PHYSICAL PROPERTIES
SUPERCONDUCTING JUNCTIONS
SUPERCONDUCTIVITY