A performance study of the hypercube parallel processor architecture
- Air Force Inst. of Tech., Wright-Patterson AFB, OH (United States)
- Florida Inst. of Tech., Melbourne, FL (United States)
This paper investigates the relationship between workload characteristics and process speedup obtainable on a hypercube parallel processor architecture. There were two goals: first was to determine the functional relationship between workload characteristics and speedup, and second was to show how simulation could be used to model the concurrently executing process to allow estimation of such a relation. The hypercube implementation used in this study was a packet-switched network with predetermined routing and a balanced computational workload. Three independent variables were controlled: total computational workload, number of processors and the message traffic load. A benchmark program was used to estimate the fundamental timing models and to validate a discrete event simulation. Results of this study are useful to software designers seeking to predict the degree of performance improvement attainable on a hypercube class machine. The methodology and results can be extended to other parallel processing architectures.
- OSTI ID:
- 6098166
- Journal Information:
- Simulation; (United States), Journal Name: Simulation; (United States) Vol. 56:3; ISSN 0037-5497; ISSN SIMUA
- Country of Publication:
- United States
- Language:
- English
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