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Title: Architecture and performance of processor-memory interconnection networks for MIMD shared memory parallel processing systems

Miscellaneous ·
OSTI ID:6091246

In this thesis the author studies the interconnection networks and their switch architectures, the performance of different architectures, under the MIMD shared memory environment, using both simulation and analytical methods. The networks he studies are constructed with a basic building block, a switch element. Quite a few alternatives are proposed in designing the switch element. Naturally, different switch architectures given different performance. He studies the performance of different switches with both analytical methods and extensive simulations. He also proposes a multiple hand shaking signal switch architecture which gives the maximum performance. Various interconnection networks and interested issues related to them are reviewed in the thesis. He proposes a new class of interconnection networks called F networks. In comparison to traditional multi-stage network, F networks provide faster communications among nodes within a cluster. Also extra routes available in the F network fault-tolerant. Based on simulations and analysis, Kruskal, Snir and Weiss established a formula for calculating network delays under moderate traffic. From his simulations the author surprisedly discovered that the Kruskal-Snir-Weiss formula holds only of the forward path delay of the networks, the return path delay is actually substantially less than the delay of the forward path. He completes the network performance formula by extending the Kruskal-Snir-Weiss formula to include the return path. He also analyzes the network performance under hot spot' traffic and obtains analytic results on the performance attained.

Research Organization:
New York Univ., NY (United States)
OSTI ID:
6091246
Resource Relation:
Other Information: Thesis (Ph.D)
Country of Publication:
United States
Language:
English