An architecture for high-performance single-chip VLSI testers
Testing is an important factor in the production of useable custom integrated circuits. Verification of the functional and AC parametric characteristics of a device are usually performed on large and expensive test systems. This thesis presents a new approach to tester architecture that seeks to greatly reduce both the size and cost of these systems. The principal idea is to base the tester design on the same high-density technology as that of the devices being tested. Through the use of novel test vector compression techniques and closed-loop timing calibration methods, high performance and high density can be achieved in a CMOS technology. The proof is the implementation of a single-chip multi-channel tester which has the size and cost attributes of the very low-end testers, yet implements many of the features found on only the most expensive machines. The high level of integration achieved results in a number of other advantages as well. The close proximity of the tester to the test device eliminates most of the signal transmission and loading issues encountered in larger systems. The extremely compact size enables in-circuit probing and performance analysis of the test device without custom fixturing. Finally, and perhaps most importantly, by implementing the tester in the same technology as that of the device to be tested, future upgrades of the tester capability can evolve along with the capabilities of the subject device.
- Research Organization:
- Stanford Univ., CA (USA)
- OSTI ID:
- 6089209
- Country of Publication:
- United States
- Language:
- English
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