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Line (block) size choice for CPU cache memories

Journal Article · · IEEE Trans. Comput.; (United States)
The line (block) size of a cache memory is one of the parameters that most strongly affects cache performance. In this paper, the author studies the factors that relate to the selection of a cache line size. The primary focus is on the cache miss ratio, but they also consider influences such as logic complexity, address tags, line crossers, I/O overruns, etc. The behavior of the cache miss ratio as a function of line size is examined carefully through the use of trace driven simulation, using 27 traces from five different machine architectures. The change in cache miss ratio as the line size varies is found to be relatively stable across workloads, and tables of this function are presented for instruction caches, data caches, and unified caches. An empirical mathematical fit is obtained. This function is used to extend previously published design target miss ratios to cover line sizes from 4 to 128 bytes and cache sizes from 32 bytes to 32K bytes; design target miss ratios are to be used to guide new machine designs. Mean delays per memory reference and memory (bus) traffic rates are computed as a function of line and cache size, and memory access time parameters. They find that for high performance microprocessor designs, line sizes in the range 16-64 bytes seem best; shorter line sizes yield high delays due to memory latency, although they reduce memory traffic somewhat. Longer line sizes are suitable for mainframes because of the higher bandwidth to main memory.
Research Organization:
Dept. of Electrical Engineering and Computer Sciences, Computer Science Div., Univ. of California, Berkeley, CA 94720
OSTI ID:
6077920
Journal Information:
IEEE Trans. Comput.; (United States), Journal Name: IEEE Trans. Comput.; (United States) Vol. C-36:9; ISSN ITCOB
Country of Publication:
United States
Language:
English