Performance of an OR-parallel logic programming system

Journal Article · Mon Feb 01 04:00:00 EST 1988 · Int. J. Parallel Program.; (United States)

DOI:https://doi.org/10.1007/BF01379323· OSTI ID:6062701

Tinker, P A

The research focus in parallel logic programming is shifting rapidly from theoretical considerations and simulation on uniprocessors to implementation on true multiprocessors. This report presents performance figures from such a system, Boplog, for OR-parallel Horn clause logic programs on the BBN Butterfly Parallel Processor. Boplog is designed expressly for a large scale shared memory multiprocessor with an Omega interconnect. The target machine and underlying execution model are described briefly. The primary focus of the paper is on detailed statistics taken from the execution of benchmark programs to assess the performance of the model and clarify the impact of design and architecture decisions. They show that while speedup of this implementation on highly OR-parallel problems is very good, overall performance is poor. Despite its speed drawback, many aspects of the implementation and its performance can prove useful in designing future systems for similar machines. A binding model that prohibits constant time access to bindings, and the inability of the machine to support an ambitious use of machine memory appear to be the most damaging factors.

• Research Organization: Rockwell International Science Center, Thousand Oaks, CA (USA)
• OSTI ID: 6062701
• Journal Information: Int. J. Parallel Program.; (United States), Journal Name: Int. J. Parallel Program.; (United States) Vol. 17:1; ISSN IJPPE
• Country of Publication: United States
• Language: English

Related Subjects

99 GENERAL AND MISCELLANEOUS
990210* -- Supercomputers-- (1987-1989)
ARRAY PROCESSORS
COMPUTER ARCHITECTURE
COMPUTERIZED SIMULATION
DATA PROCESSING
DESIGN
ELECTRONIC CIRCUITS
IMPLEMENTATION
MATHEMATICAL LOGIC
MATHEMATICAL MODELS
MATHEMATICS
MEMORY DEVICES
PARALLEL PROCESSING
PERFORMANCE TESTING
PROCESSING
PROGRAMMING
SIMULATION
STATISTICS
SWITCHING CIRCUITS
TASK SCHEDULING
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