Partitioning, placement, and routing algorithms for high-complexity integrated circuits
Advances in technology have allowed system designers to implement integrated circuits of high complexity, involving more than one million transistors, on a single chip. The task of designing such complex circuits has created a need for layout algorithms with higher execution speed and more efficient use of computer memory. In this thesis, new partitioning, placement, and routing algorithms are proposed, which exhibit extraordinary performance in terms of design quality, runtime, and memory efficiency. The main features of these algorithms are their simultaneous treatment of all modules and all nets, and exploitation of the sparsity of circuit networks in the data representation. The algorithms are applicable to large scale designs, with which most conventional algorithms have difficulties. A unified approach to the partitioning and one-dimensional placement problems is proposed. The approach is based on the minimization of a quadratic function of the total wire length between modules subject to slot constraints, which ensure that each module is assigned to one of a set of discrete locations. For the case in which all modules are movable, an eigenvector approach is used. For the case in which some modules are fixed, the problem is converted to a system of linear equations. A hierarchical two-dimensional placement method, based on this unified approach, is presented. A linear system is solved to obtain a tentative global placement which does not yet satisfy the slot constraints. The chip is then partitioned into subblocks and a linear system is solved for each subblock to obtain a new placement in the subblock. A technique, similar to the Block Gauss-Seidel technique for solving linear systems, is used to communicate information about updated placement in one subblock to neighboring subblocks. The process is repeated with finer partitions until the slot constraints are satisfied.
- Research Organization:
- California Univ., Berkeley, CA (USA)
- OSTI ID:
- 6054017
- Country of Publication:
- United States
- Language:
- English
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