The SLAC scanner processor: A FASTBUS for data collection and processing

Conference · Fri Feb 01 04:00:00 EST 1985 · IEEE Trans. Nucl. Sci.; (United States)

OSTI ID:6006592

Brafman, H; Glanzman, T; Lankford, A J; Olsen, J; Paffrath, L

A new, general purpose, programmable FASTBUS module, the SLAC Scanner Processor (SSP), is introduced. Both hardware and software elements of SSP operation are discussed. The role of the SSP within the upgraded Mark II Detector at SLAC is described. The SLAC Scanner Processor (or SSP) is a general-purpose, high-speed, programmable FASTBUS master. It has been designed for crate-level readout and processing of data from TDC and FADC modules which instrument a new 6000-wire central drift chamber for the upgraded Mark II detector. The SSP, however, provides a general and powerful means of moving and processing data in a FASTBUS system. Therefore, it has also been adopted by the Mark II for use at the system-level as a cable-segment master and buffer module.

• Research Organization: Stanford Linear Accelerator Center, Stanford, CA
• OSTI ID: 6006592
• Report Number(s): CONF-841007-
• Conference Information: Journal Name: IEEE Trans. Nucl. Sci.; (United States) Journal Volume: NS-32:1
• Country of Publication: United States
• Language: English

Related Subjects

43 PARTICLE ACCELERATORS
430303* -- Particle Accelerators-- Experimental Facilities & Equipment
COMPUTERS
DATA ACQUISITION
DATA PROCESSING
DIGITAL COMPUTERS
DRIFT CHAMBERS
EQUIPMENT INTERFACES
FASTBUS SYSTEM
MEASURING INSTRUMENTS
MULTIWIRE PROPORTIONAL CHAMBERS
NATIONAL ORGANIZATIONS
PROCESSING
PROPORTIONAL COUNTERS
RADIATION DETECTORS
STANFORD LINEAR ACCELERATOR CENTER
US DOE
US ERDA
US ORGANIZATIONS