Performance analysis of the FFT algorithm on a shared-memory parallel architecture

Journal Article · Wed Jul 01 04:00:00 EDT 1987 · IBM J. Res. Dev.; (United States)

DOI:https://doi.org/10.1147/rd.314.0435· OSTI ID:5912399

Cvetanovic, Z

This paper presents a model for the performance prediction of FFT algorithms executed on a shared-memory parallel computer consisting of N processors and the same number of memory modules. The model applies a deterministic analysis to estimate the communication delay through the interconnection network by assuming that all requests arrive at the network in bursts. The results indicate that the communication delay is significantly affected by the method applied to allocate data to memory modules. For the case in which all data items referenced by a processor during an iteration are allocated to a single memory module. The authors present the best and worst case.

• Research Organization: Digital Equipment Corp., 85 Swanson Road, Boxborough, MA 01719
• OSTI ID: 5912399
• Journal Information: IBM J. Res. Dev.; (United States), Journal Name: IBM J. Res. Dev.; (United States) Vol. 31:4; ISSN IBMJA
• Country of Publication: United States
• Language: English

Related Subjects

99 GENERAL AND MISCELLANEOUS
990210* -- Supercomputers-- (1987-1989)
ALGORITHMS
ARRAY PROCESSORS
COMMUNICATIONS
COMPUTER ARCHITECTURE
COMPUTERIZED SIMULATION
COMPUTERS
DATA TRANSMISSION
DIGITAL COMPUTERS
EFFICIENCY
FOURIER TRANSFORMATION
INTEGRAL TRANSFORMATIONS
MATHEMATICAL LOGIC
MEMORY DEVICES
PARALLEL PROCESSING
PERFORMANCE
PROGRAMMING
SIMULATION
SUPERCOMPUTERS
TRANSFORMATIONS