Fastbus host interface for VAX/VMS

Journal Article · Mon Jan 31 23:00:00 EST 1983 · IEEE Trans. Nucl. Sci.; (United States)

DOI:https://doi.org/10.1109/TNS.1983.4332250· OSTI ID:5828387

Siskind, E J

A list processing microprocessor controlled host interface for FASTBUS has been constructed by connection of a FASTBUS cable segment to the VAX DR-32 Device Interconnect (DDI) implemented via the DEC DR-780 channel on a VAX-11/780 system. Block transfer rates of 5.7 megabytes/second (700 ns per 32 bit longword) are achieved on VAX-11/780 systems equipped with a single MS-780 memory controller, while interleaved dual memory controller systems reach 8.0 megabytes/second (500 ns per longword) performance. The hardware and software interface should work equally well on DR-750 equipped VAX-11/750 systems (with appropriate reductions in achievable bandwidth) as well as on any future VAX systems equipped with a DDI adapter.

• Research Organization: NYCB Real-Time Computing, Rocky Point, NY 11778
• OSTI ID: 5828387
• Journal Information: IEEE Trans. Nucl. Sci.; (United States), Journal Name: IEEE Trans. Nucl. Sci.; (United States) Vol. 30:1; ISSN IETNA
• Country of Publication: United States
• Language: English

Related Subjects

99 GENERAL AND MISCELLANEOUS
990300* -- Information Handling
COMPUTERIZED CONTROL SYSTEMS
COMPUTERS
CONTROL SYSTEMS
DEC COMPUTERS
ELECTRONIC CIRCUITS
EQUIPMENT INTERFACES
FASTBUS SYSTEM
IMPLEMENTATION
MEMORY DEVICES
MICROELECTRONIC CIRCUITS
MICROPROCESSORS
PERFORMANCE