Using program structure to achieve prefetching for cache memories
A concise program structure notation, called a program skeleton, is developed that can be used for program analysis or, if machine-specific details are included, for memory prefetching. The program skeleton describes the structure of the source code as well as the low-level accessing behavior. Transformations are developed to create a machine-specific cache memory prefetching control program, called the prefetch skeleton (PFS), from the program skeleton. A prefetching unit (PFU) is developed as a simple in-cache processor. The PFU executes the PFS and generates cache line prefetch requests ahead of CPU demand requests. A variety of PFS-cache machines are simulated in detail to demonstrate the feasibility of the PFS prefetcher. Instruction miss delays can be reduced significantly by using a PFS-cache. Some reduction in data miss delays is also obtained even though the PFS as developed in this initial research focuses primarily on instruction prefetching. The PFS prefetching scheme improves cache performance without requiring programmer involvement, since the PFS is generated automatically by the compiler as it compiles the source program. The PFS concept is compatible with a variety of programming languages. The PFS-cache machine is capable of running non-PFS programs, although better performance is obtained when the programs are recompiled to create the PFS. 8 refs., 28 figs., 22 tabs.
- Research Organization:
- Illinois Univ., Urbana (USA). Center for Supercomputing Research and Development
- DOE Contract Number:
- FG02-85ER25001
- OSTI ID:
- 5735048
- Report Number(s):
- DOE/ER/25001-43; UILU-ENG-87-8001; CSRD-647; ON: DE88003599
- Resource Relation:
- Other Information: Thesis (Ph.D.). Portions of this document are illegible in microfiche products
- Country of Publication:
- United States
- Language:
- English
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