Timing and control requirements for a 32-channel AMU-ADC ASIC for the PHENIX detector

Technical Report · Sat Jan 31 23:00:00 EST 1998

DOI:https://doi.org/10.2172/570172· OSTI ID:570172

Emery, M S; Ericson, M N; Britton, Jr, C L ^[1]

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1. and others

A custom CMOS Application Specific Integrated Circuit (ASIC) has been developed consisting of an analog memory unit (AMU) has been developed consisting of an analog memory unit (AMU) and analog to digital converter (ADC), both of which have been designed for applications in the PHENIX experiment. This IC consists of 32 pipes of analog memory with 64 cells per pipe. Each pipe also has its own ADC channel. Timing and control signal requirements for optimum performance are discussed in this paper.

• Research Organization: Oak Ridge National Lab., TN (United States)
• Sponsoring Organization: USDOE Assistant Secretary for Human Resources and Administration, Washington, DC (United States)
• DOE Contract Number: AC05-96OR22464
• OSTI ID: 570172
• Report Number(s): ORNL/CP--95612; ON: DE98001894
• Country of Publication: United States
• Language: English

Related Subjects

42 ENGINEERING
43 PARTICLE ACCELERATORS
ANALOG-TO-DIGITAL CONVERTERS
CONTROL
INTEGRATED CIRCUITS
MEMORY DEVICES
OPERATION
PERFORMANCE
SHOWER COUNTERS
TIMING CIRCUITS