Binary peak power multiplier and its application to linear accelerator design

Journal Article · Wed Oct 01 00:00:00 EDT 1986 · IEEE Trans. Microwave Theory Tech.; (United States)

DOI:https://doi.org/10.1109/TMTT.1986.1133493· OSTI ID:5657354

Farkas, Z D

This paper describes a new method of pulse compression, the binary power multiplier (BPM), a device which multiplies RF power in binary steps. It comprises one or more stages, each of which doubles the input power and halves the input pulse length. Practical designs are described and expressions for their compression efficiency are derived. The usefulness of pulse compression for accelerator design is illustrated and compared with the pulse compression system currently in use at the Stanford Linear Accelerator Center.

• Research Organization: Stanford Linear Accelerator Center, Stanford Univ., Stanford, CA 94305
• DOE Contract Number: AC03-76SF00515
• OSTI ID: 5657354
• Journal Information: IEEE Trans. Microwave Theory Tech.; (United States), Journal Name: IEEE Trans. Microwave Theory Tech.; (United States) Vol. MTT-34:10; ISSN IETMA
• Country of Publication: United States
• Language: English

Related Subjects

43 PARTICLE ACCELERATORS
430100* -- Particle Accelerators-- Design
Development
& Operation
ACCELERATORS
COMPRESSION
DESIGN
LINEAR ACCELERATORS
PEAK LOAD
PULSES