Simulation and performance analysis of interprocessor communication mechanism for MIMD system

Thesis/Dissertation · Fri Jan 01 04:00:00 EST 1988

OSTI ID:5635040

Kim, J H

The architecture and a high-level implementation of a multiple instruction stream-multiple data stream (MIMD) parallel processor system are specified; a simulator is developed to support design and evaluation of systems based on the architecture; and experiments are conducted with the simulator to evaluate system performance. The architecture, a significant extension of the horizontal/vertical-bas (H/V-bus) system architecture, features a highly concurrent interprocessor communication mechanism (IPC mechanism) to support applications in continuous system simulation and related scientific areas. The architecture provides an N {times} N array of processing elements (PEs) that communicate with each other through a network of N horizontal buses and N vertical buses; for each bus there is a separate bus controller that controls operations on the bus. The simulator, written in SLAM II and FORTRAN, is designed to provide high-resolution - to the level of the clock periods of individual components - in simulating the IPC mechanism and lower resolution-to the level of execution times of machine-language instruction-in stimulating processing elements. Parameters provide the user with independent control of system size, PE speed, IPC-mechanism speed, and floating-point-arithmetic speed.

• Research Organization: Arizona Univ., Tucson, AZ (USA)
• OSTI ID: 5635040
• Country of Publication: United States
• Language: English

Related Subjects

99 GENERAL AND MISCELLANEOUS
990210* -- Supercomputers-- (1987-1989)
ARRAY PROCESSORS
COMMUNICATIONS
COMPUTER ARCHITECTURE
COMPUTERIZED SIMULATION
PARALLEL PROCESSING
PERFORMANCE
PROGRAMMING
SIMULATION