Reconfigurable multipipelines for vector supercomputers
- University of Southern California, Los Angeles, CA (USA). Dept. of Electrical Engineering
- Instituto di Informatica, Universita degli Studi di Trento, 38100 Trento (IT)
- State Univ. of New York, Stony Brook, NY (USA). Dept. of Computer Science
Supercomputers typically use pipelines in their processors for achieving high performance. These pipelines consist of several stages and many such identical pipelines are used in vector supercomputers for doing vector operations. This paper addresses the problem of recovering multipipelines in the presence of faulty stages. The stages are assumed to be organized in rows and columns. The authors alternate the pipeline stages with reconfiguring circuitry which is used for bypassing the faulty stages. The pipelines are configured by programming the switches in a distributed manner using fault information available locally. The reprogrammability of the switches enables them to tolerate dynamic faults. Their configuration algorithm is optimal in the sense that it recovers the maximum number of pipelines under any fault pattern. Probabilistic bounds on the delay (the number of bypassed faulty stages) and yield (the number of nonfaulty pipelines recovered) are derived. They show that the maximum signal delay in any of the pipelines is {theta}(logm), where m is the initial number of pipelines.
- OSTI ID:
- 5549567
- Journal Information:
- IEEE (Institute of Electrical and Electronics Engineers) Transactions on Computers; (USA), Vol. 38:9; ISSN 0018-9340
- Country of Publication:
- United States
- Language:
- English
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