skip to main content
OSTI.GOV title logo U.S. Department of Energy
Office of Scientific and Technical Information

Title: System theoretic models for high-density VLSI (very large scale integration) structures. Final technical report

Abstract

This research project involved the development of mathematical models for analysis, synthesis, and simulation of large systems of interacting devices. The work was motivated by problems that may become important in high-density VLSI chips with characteristic feature sizes less than 1 micron: it is anticipated that interactions of neighboring devices will play an important role in the determination of circuit properties. It is hoped that the combination of high device densities and such local interactions can somehow be exploited to increase circuit speed and to reduce power consumption. To address these issues from the point of view of system theory, research was pursued in the areas of nonlinear and stochastic systems and into neural-network models. Statistical models were developed to characterize various features of the dynamic behavior of interacting systems. Random-process models for studying the resulting asynchronous modes of operation were investigated. The local interactions themselves may be modeled as stochastic effects. The resulting behavior was investigated through the use of various scaling limits, and by a combination of other analytical and simulation techniques. Techniques arising in a variety of disciplines where models of interaction have been formulated and explored were considered and adapted for use.

Authors:
;
Publication Date:
Research Org.:
Princeton Univ., NJ (USA). Dept. of Electrical Engineering and Computer Science
OSTI Identifier:
5549382
Report Number(s):
AD-A-209901/8/XAB
Resource Type:
Technical Report
Country of Publication:
United States
Language:
English
Subject:
99 GENERAL AND MISCELLANEOUS//MATHEMATICS, COMPUTING, AND INFORMATION SCIENCE; 42 ENGINEERING; INTEGRATED CIRCUITS; SYSTEMS ANALYSIS; ENERGY CONSUMPTION; MATHEMATICAL MODELS; OPERATION; PROGRESS REPORT; SIMULATION; STOCHASTIC PROCESSES; VELOCITY; DOCUMENT TYPES; ELECTRONIC CIRCUITS; MICROELECTRONIC CIRCUITS 990210* -- Supercomputers-- (1987-1989); 420800 -- Engineering-- Electronic Circuits & Devices-- (-1989)

Citation Formats

Dickinson, B.W., and Hopkins, W.E.. System theoretic models for high-density VLSI (very large scale integration) structures. Final technical report. United States: N. p., 1989. Web.
Dickinson, B.W., & Hopkins, W.E.. System theoretic models for high-density VLSI (very large scale integration) structures. Final technical report. United States.
Dickinson, B.W., and Hopkins, W.E.. 1989. "System theoretic models for high-density VLSI (very large scale integration) structures. Final technical report". United States. doi:.
@article{osti_5549382,
title = {System theoretic models for high-density VLSI (very large scale integration) structures. Final technical report},
author = {Dickinson, B.W. and Hopkins, W.E.},
abstractNote = {This research project involved the development of mathematical models for analysis, synthesis, and simulation of large systems of interacting devices. The work was motivated by problems that may become important in high-density VLSI chips with characteristic feature sizes less than 1 micron: it is anticipated that interactions of neighboring devices will play an important role in the determination of circuit properties. It is hoped that the combination of high device densities and such local interactions can somehow be exploited to increase circuit speed and to reduce power consumption. To address these issues from the point of view of system theory, research was pursued in the areas of nonlinear and stochastic systems and into neural-network models. Statistical models were developed to characterize various features of the dynamic behavior of interacting systems. Random-process models for studying the resulting asynchronous modes of operation were investigated. The local interactions themselves may be modeled as stochastic effects. The resulting behavior was investigated through the use of various scaling limits, and by a combination of other analytical and simulation techniques. Techniques arising in a variety of disciplines where models of interaction have been formulated and explored were considered and adapted for use.},
doi = {},
journal = {},
number = ,
volume = ,
place = {United States},
year = 1989,
month = 1
}

Technical Report:
Other availability
Please see Document Availability for additional information on obtaining the full-text document. Library patrons may search WorldCat to identify libraries that may hold this item. Keep in mind that many technical reports are not cataloged in WorldCat.

Save / Share:
  • This report covers the period from April 1, 1985 through September 30, 1985. The research discussed here is described in more detail in several published and unpublished reports cited. The CAD frame Schema has progressed to the point where it is useful for ample chip designs. The interface to CIF is complete, and work has begun on importing layout libraries. An interface to EDIF is being installed. Simulators can now be connected, and thought is going into organization of VLSI libraries. A plan for the distribution of Schema is now being worked out. Members of the DARPA VLSI community willmore » be able to get copies in the Fall of 1985 or Spring of 1986. Previous results on waveform bounding have been generalized to large classes of problems described in canonical control-theory form. Work has begun on models for interconnect taking account of line inductance. This domain is less general that RLC networks, and there is hope that some of the previously derived bounds still apply. Indeed, some such results are reported here. During this period a novel device, the UV write-enabled PROM, was reported at a conference. Work continues on developing useful circuits employing this device.« less
  • Since its inception, VLSI theory has expanded in many fruitful and interesting directions. One major branch is layout theory, which studies the efficiency with which graphs can be embedded in the plane according to VLSI design rules. This survey paper, reviews some of the major accomplishments of VLSI layout theory and discuss how layout theory engendered the notion of area and volume-universal networks, such as fat-trees. These scalable networks offer a flexible alternative to the more-common hypercube-based networks for interconnecting the processors of large parallel supercomputers.
  • A high-performance, cost-effective silicon-on-insulator (SOI) technology would have important near-term applications in radiation-hardened electronics and longer-term applications in submicrometer VLSI. The advantages of SOI over bulk Si technology for these applications are outlined, and CMOS, CJFET, and bipolar device structures being developed for SOI are discussed. The current status and future prospects of the two most promising SOI technologies -- beam recrystallization and high-dose oxygen implantation -- are reviewed, with emphasis on such issues critical to commercialization as material quality and manufacturing feasibility.
  • The use of VLSI technology to build supercomputers is analyzed in depth. The benefits of VLSI are reviewed, and the liabilities are explored thoroughly. The perimeter problem and the planarity problem are identified as being critical limits on architectural design. The CHiP architecture, a highly parallel computer designed with VLSI implementation in mind, is scrutinized in terms of how well it exploits the benefit fo VLSI and how well it avoids the liabilities. Not surprisingly, it does pretty well.
  • A generalization of a known class of parallel sorting algorithms is presented, together with a new architecture to execute them. A VLSI implementation is also proposed, and its area-time performance is discussed. It is shown that an algorithm in the class is executable in 0(logn) time by a chip occupying O(n2) area. The design is a typical instance of a 'hybrid architecture', resulting from the combination of well-known VLSI arrays as the orthogonal-trees and the cube-connected-cycles; it is also the first known to meet the AT21 = omega(n2log2n) lower bound for sorters of n words of length (1 + epsilon)more » and working in minimum 0(logn) time.« less