A simulation study of decoupled architecture computers

Journal Article · Fri Aug 01 00:00:00 EDT 1986 · IEEE Trans. Comput.; (United States)

DOI:https://doi.org/10.1109/TC.1986.1676820· OSTI ID:5449329

Smith, J S; Weiss, S; Pang, N Y

Decoupled architectures achieve high scalar performance by cleanly splitting instruction processing into memory access and execution tasks. Several decoupled architectures have been proposed, and they all have two characteristics in common: 1) they have two separate sets of instructions, one for accessing memory and one for performing function execution. 2) The memory accessing task and the execution task communicate via architectural queues. These characteristics lead to pipelined computer that have the following advantages: 1) they can issue more than one instruction per clock period; 2) they can dynamically schedule instructions at runtime; 3) they are less sensitive to memory access delays than conventional architectures. The authors present a simulation study of decoupled architectures. The simulation models are very detailed, with timing resolution to the clock period. The Lawrence Livermore Loops are used as the workload. They first describe a decoupled architecture based on the CRAY-1 scalar architecture. The sensitivity to memory access delays are studied by varying memory access time over a wide range of values. They show that performance improvements increase linearly over the scalar CRAY-1 as the memory access paths of both are lengthened. Then, they study queue lengths in decoupled machines, and show the affect of queue lengths on performance. Relatively short queues are shown to give optimum, or near-optimum, performance.

• Research Organization: Astronautics Corp. of America, Madison, WI
• OSTI ID: 5449329
• Journal Information: IEEE Trans. Comput.; (United States), Vol. C-35:8
• Country of Publication: United States
• Language: English

Related Subjects

99 GENERAL AND MISCELLANEOUS//MATHEMATICS, COMPUTING, AND INFORMATION SCIENCE
CRAY COMPUTERS
ARCHITECTURE
COMPUTERIZED SIMULATION
DATA-FLOW PROCESSING
DATA PROCESSING
LAWRENCE LIVERMORE LABORATORY
MEMORY DEVICES
OPTIMIZATION
PERFORMANCE
QUEUES
SUPERCOMPUTERS
TASK SCHEDULING
TIME DEPENDENCE
COMPUTERS
DIGITAL COMPUTERS
NATIONAL ORGANIZATIONS
PROCESSING
PROGRAMMING
SIMULATION
US AEC
US DOE
US ERDA
US ORGANIZATIONS
990200* - Mathematics & Computers