Graph theoretical analysis and design of multistage interconnection networks

Journal Article · Fri Jul 01 00:00:00 EDT 1983 · IEEE Trans. Comput.; (United States)

DOI:https://doi.org/10.1109/TC.1983.1676295· OSTI ID:5365007

Agrawal, D P

This paper introduces two graph theoretic models that provide a uniform procedure for analyzing 2/sup n/-input/2/sup n/-output multistage interconnection networks (MIN's), implemented with 2-input/2-output switching elements (SES) and satisfying a characteristic called the buddy property. These models show that all such n-stage MINs are topologically equivalent and hence prove that one MIN can be implemented from integrated circuits designed for another MIN. The proposed techniques also allow identical modeling and comparison of permutation capabilities of n-stage MINs and other link-controlled networks like augmented data manipulator and SW Banyan network and hence, allows comparison of their permutation. In the case of any conflict in the MIN, an upper bound for the required number of passes has been obtained. 32 references.

• Research Organization: Wayne State Univ., Detroit, MI
• OSTI ID: 5365007
• Journal Information: IEEE Trans. Comput.; (United States), Vol. 7
• Country of Publication: United States
• Language: English

Related Subjects

99 GENERAL AND MISCELLANEOUS//MATHEMATICS, COMPUTING, AND INFORMATION SCIENCE
COMPUTER NETWORKS
DESIGN
PARALLEL PROCESSING
PROGRAMMING
990200* - Mathematics & Computers