Concurrent architectures for two-dimensional recursive digital filtering
- Minnesota Univ., Minneapolis, MN (USA). Dept. of Electrical Engineering
- California Univ., Berkeley, CA (USA). Dept. of Electrical Engineering and Computer Sciences
This paper presents new efficient architectures for high-speed implementation of direct form and local state-space form two-dimensional recursive digital filters. Unlike one-dimensional recursive systems, two-dimensional recursive digital filter algorithms possess a large amount of inherent concurrency, which can be exploited for fine-grain pipelining and/or parallelism. The locus of these concurrent computations is referred to as the concurrent computation region. The authors exploit this concurrency to derive fine-grain pipelined and one-dimensional block architectures for implementation of two-dimensional recursive digital filters by appropriate interleaving (or indexing) of the input samples, without requiring any algorithm transformation and without any hardware overhead. They extend the look-ahead computation and incrementation computation techniques to two dimensions, and use these to derive new two-dimensional incremental block filter architectures. The multiplication complexity of their two-dimensional incremental block filter is compared to that of existing block structures. Fine-grain pipelined two-dimensional block structures are presented. The index mapping functions are used to derive delay operators for various architectures.
- OSTI ID:
- 5346243
- Journal Information:
- IEEE (Institute of Electrical and Electronics Engineers) Transactions on Circuits and Systems; (USA), Journal Name: IEEE (Institute of Electrical and Electronics Engineers) Transactions on Circuits and Systems; (USA) Vol. 36:6; ISSN 0098-4094; ISSN ICSYB
- Country of Publication:
- United States
- Language:
- English
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