Architectures for two-dimensional lattice computations with linear speedup

Thesis/Dissertation · Fri Jan 01 00:00:00 EST 1988

OSTI ID:5214173

Kugelmass, S D

Many problems are characterized by the fact that they deal with data values distributed on a regular mesh, or lattice. They arise in a wide variety of applications such as image processing, computer vision, the solution of partial differential equations, and the simulation of cellular automata. This dissertation explores theoretical and practical questions in the design of massively parallel machines for lattice processing. The author analyzes and compares two architectures that are efficient for lattice computations and are suitable for VLSI implementation: the linear array, and a block-partitioned architecture proposed by Sternberg. These architectures have a property called linear speedup. This is, n processors of fixed size and cost provide n times the throughput of one processor on the same problem instance. He finds that the linear pipelined array is the more attractive of the two architectures for a two-dimensional lattice machine, because of its great simplicity. He next studies the effect of clock skew as a possible limitation on the ultimate performance of large, globally synchronized multiprocessing systems. He proposes and analyzes a probabilistic model for clock-skew accumulation based on variations in buffer and wire delays.

• Research Organization: Princeton Univ., NJ (USA)
• OSTI ID: 5214173
• Resource Relation: Other Information: Thesis (Ph. D.)
• Country of Publication: United States
• Language: English

Related Subjects

99 GENERAL AND MISCELLANEOUS//MATHEMATICS, COMPUTING, AND INFORMATION SCIENCE
ARRAY PROCESSORS
MESH GENERATION
COMPUTER CALCULATIONS
PARALLEL PROCESSING
COMPUTER ARCHITECTURE
VECTOR PROCESSING
INTEGRATED CIRCUITS
ELECTRONIC CIRCUITS
MICROELECTRONIC CIRCUITS
PROGRAMMING
990200* - Mathematics & Computers