Cray-class multiprocessor simulator. Technical report
Technical Report
·
OSTI ID:5208124
A logical-timing instruction-level simulator is described for a hypothetical multiprocessor consisting of CRAY-1's connected to a common memory. It is useful for gaining insight into the design of multiprocessor algorithms and for developing high performance algorithms for CRAY processors with instruction sets similar to the CRAY-1.
- Research Organization:
- Michigan Univ., Ann Arbor (USA). Supercomputer Algorithm Research Lab.
- OSTI ID:
- 5208124
- Report Number(s):
- AD-A-136555/0
- Country of Publication:
- United States
- Language:
- English
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