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U.S. Department of Energy
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Array and parallel processors in on-line computations. Final report

Technical Report ·
OSTI ID:5152480
This report presents a classification of parallel processors and discusses previous EPRI-sponsored work indicating that the array processor holds special promise for use in power systems simulation problems. Operating on this premise a complete ac power flow code was developed for the Floating Point Systems AP-120B array processor and its host computer. This optimized code will solve the IEEE standard 118-bus power flow in less than 2.5 ms. from a flat start and can be reasonably projected to solve a 1000-bus power flow in less than 0.5 second. Computational speed of this order allows problems such as on-line contingency studies to be solved. Up until now these solutions were inaccessible due to the expense of the equipment required. The performance of a parallel connection of several array processors has also been studied. The results show that a rather simple configuration of several processing elements resembling the AP-120B will operate with a speedup close to the number of processors involved.
Research Organization:
Cornell Univ., Ithaca, NY (USA). School of Electrical Engineering
OSTI ID:
5152480
Report Number(s):
EPRI-EL-2363; ON: DE82903572
Country of Publication:
United States
Language:
English