Network architecture for OPS5
Conference
·
OSTI ID:5152375
The design and implementation of a non-Rete based architecture which captures some of the inherent parallelism in the OPS5 expert system language are discussed. A central feature of the architecture is a network bus over which a single host processor broadcasts messages to a set of parallel rule processors. This transmit-only bus is implented by a memory-mapped shceme which permits the rule processors to be decoded in parallel. All OPS5 rule matching processes and most of those associated with conflict resolution are executed by the parallel rule processors. The host performs the tasks associated with the firing of a selected rule. Performance data are presented for the prototype system which comprise a hot processor and 64 parallel rule processors, each embodying a Motorola MC68000 microprocessor and 512 kbytes of unshared memory. 6 refs., 4 figs.
- Research Organization:
- Oak Ridge National Lab., TN (USA)
- DOE Contract Number:
- AC05-84OR21400
- OSTI ID:
- 5152375
- Report Number(s):
- CONF-880540-1; ON: DE88002802
- Country of Publication:
- United States
- Language:
- English
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