Design methodology for multiprocessor architecture

Thesis/Dissertation · Fri Jan 01 04:00:00 EST 1988

OSTI ID:5145961

Lee, P W

This work analyzes one basic cycle of a digital-signal-processing algorithm. The intertask buffering requirements and the number of executions of each task during one basic cycle are determined using a graph theoretical algorithm which exhibits linear complexity. Also, task precedence relationships are generated within a scheduling cycle which is made up of any integral number of basic cycles. The capability of combining a number of basic cycles into a scheduling cycle are shown to increase the processor utilization factor and, in turn, the computational throughput. It is shown that these results can be utilized to generate a fixed schedule on an N-processor architecture where the number of processors is an input variable. The parallel efficiency of the algorithm when executing on an N-processor architecture is then determined from the average processor utilization factor. The nonexistence of optimum schedules for the general case prompts a discussion of scheduling methodologies. The complexity of the algorithms introduced are analyzed, and, finally, the applications of this work to analysis and design of digital-signal-processing algorithms and the associated multiprocessor hardware is discussed. The appendices contain an example of a design session using the methodology outlined in this thesis.

• Research Organization: Rutgers--the State Univ., New Brunswick, NJ (USA)
• OSTI ID: 5145961
• Country of Publication: United States
• Language: English

Related Subjects

99 GENERAL AND MISCELLANEOUS
990200* -- Mathematics & Computers
ALGORITHMS
ARRAY PROCESSORS
COMPUTER ARCHITECTURE
DATA PROCESSING
DATA-FLOW PROCESSING
DESIGN
EFFICIENCY
MATHEMATICAL LOGIC
PARALLEL PROCESSING
PROCESSING
PROGRAMMING
TASK SCHEDULING