A DELAY LINE MEMORY SYSTEM FOR THE HIGH COUNTING RATE PULSE HEIGHT ANALYZER (in Japanese)
A delay line memory system to be used with a pulse height analyzer capable of analyzing several pulses during one memory cycle is described. The synchronizing pulse generator generates a synchronizing pulse, which is circulated along the delay line and gives a reference of phase, so that the pulses in each channel of the memory will come out in phase with the addition signals from the binary converter. In the write-in circuit, the output pulse of the adder modulates a carrier of 15 Mc, and this modulated pulse is applied to the input transducer of the delay line. The output transducer of the delay line gives a delayed modulated pulse about 70 db below the level of the input. The read-out circuit consists of an amplifier, a detector, and a pulse shaping circuit and compensates for the loss in the delay line and the transducers and reshapes the pulse waveform. In the digit and channel pulse generating circuit, the synchronizing pulse starts a pulsed oscillator that generates a pulse train of 1011 pulses. The decimal counter gives a channei pulse for every ten digit pulses. The binary converter and the adder are the most important components of the system. When two or more pulses of the same height are analyzed during one memory cycle, two or more must be added to the content of the corresponding channel in the memory. The binary converter converts the binary expression of the number to be added into a corresponding series of pulses. The output of the binary converter and the content of the memory are added together in this circuit, which gives the sum as its output. (JAIF)
- Research Organization:
- Tokyo Univ.
- NSA Number:
- NSA-17-030105
- OSTI ID:
- 4698846
- Journal Information:
- Proc. Japan Conf. Radioisotopes, Vol. Vol: 5th, No. 3; Other Information: Orig. Receipt Date: 31-DEC-63
- Country of Publication:
- Country unknown/Code not available
- Language:
- Japanese
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