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Title: Method of pedestal and common-mode noise correction for switched-capacitor analog memories

Abstract

A method and apparatus are disclosed for correcting common-mode noise and pedestal noise in a multichannel array of switched-capacitor analog memories wherein each analog memory is connected to an associated analog-to-digital converter. The apparatus comprises a single differential element in two different embodiments. In a first embodiment, the differential element is a reference analog memory connected to a buffer. In the second embodiment, the differential element is a reference analog memory connected to a reference analog-to-digital connected to an array of digital summing circuits. 4 figs.

Inventors:
Publication Date:
Research Org.:
Lockheed Martin Energy Syst Inc
OSTI Identifier:
415753
Patent Number(s):
US 5,590,104/A/
Application Number:
PAN: 8-316,193
Assignee:
Martin Marietta Energy Systems, Inc., Oak Ridge, TN (United States)
DOE Contract Number:  
AC05-84OR21400
Resource Type:
Patent
Resource Relation:
Other Information: PBD: 31 Dec 1996
Country of Publication:
United States
Language:
English
Subject:
42 ENGINEERING NOT INCLUDED IN OTHER CATEGORIES; 44 INSTRUMENTATION, INCLUDING NUCLEAR AND PARTICLE DETECTORS; ANALOG SYSTEMS; MEMORY DEVICES; CORRECTIONS; NOISE; ANALOG-TO-DIGITAL CONVERTERS; DIGITAL CIRCUITS

Citation Formats

Britton, C L. Method of pedestal and common-mode noise correction for switched-capacitor analog memories. United States: N. p., 1996. Web.
Britton, C L. Method of pedestal and common-mode noise correction for switched-capacitor analog memories. United States.
Britton, C L. Tue . "Method of pedestal and common-mode noise correction for switched-capacitor analog memories". United States.
@article{osti_415753,
title = {Method of pedestal and common-mode noise correction for switched-capacitor analog memories},
author = {Britton, C L},
abstractNote = {A method and apparatus are disclosed for correcting common-mode noise and pedestal noise in a multichannel array of switched-capacitor analog memories wherein each analog memory is connected to an associated analog-to-digital converter. The apparatus comprises a single differential element in two different embodiments. In a first embodiment, the differential element is a reference analog memory connected to a buffer. In the second embodiment, the differential element is a reference analog memory connected to a reference analog-to-digital connected to an array of digital summing circuits. 4 figs.},
doi = {},
journal = {},
number = ,
volume = ,
place = {United States},
year = {1996},
month = {12}
}