A mean value analysis multiprocessor model incorporating superscalar processors and latency tolerating techniques
Journal Article
·
· International Journal of Parallel Programming
OSTI ID:273923
- Univ. of Massachusettes, Amherst, MA (United States)
Several approximate Mean Value Analysis (MVA) shared memory multiprocessor models have been developed and used to evaluate a number of system architectures. In recent years, the use of superscalar processors, multilevel cache hierarchies, and latency tolerating techniques has significantly increased the complexity of multiprocessor system modeling. We present an analytical performance model which extends previous multiprocessor MVA models by incorporating these new features and in addition, increases the level of modeling detail to improve flexibility and accuracy. The extensions required to analyze the impact of these new features are described in detail. We then use the model to demonstrate some of the tradeoffs involved in designing modern multiprocessors, including the impact of highly superscalar architectures on the scalability of multiprocessor systems.
- OSTI ID:
- 273923
- Journal Information:
- International Journal of Parallel Programming, Journal Name: International Journal of Parallel Programming Journal Issue: 3 Vol. 24; ISSN IJPPE5; ISSN 0885-7458
- Country of Publication:
- United States
- Language:
- English
Similar Records
Development and Validation of a Hierarchical Memory Model Incorporating CPU- and Memory-Operation Overlap
A mean-value performance analysis of a new multiprocessor architecture
Can high bandwidth and latency justify large cache blocks in scalable multiprocessors?
Conference
·
Tue Dec 30 23:00:00 EST 1997
·
OSTI ID:621718
A mean-value performance analysis of a new multiprocessor architecture
Book
·
Thu Dec 31 23:00:00 EST 1987
·
OSTI ID:6888772
Can high bandwidth and latency justify large cache blocks in scalable multiprocessors?
Conference
·
Fri Dec 30 23:00:00 EST 1994
·
OSTI ID:98914