A sub-5 ps jitter time-to-digital converter ASIC with back-gate delay tuning in 22 nm CMOS

Quinn, Adam; Xie, Si; Apreysan, Artur; Fahim, Farah; Los, Sergey; Peña, Cristián; Lara, Carlos Eugenio Perez; Zimmerman, Tom; Braga, Davide

doi:10.1016/j.nima.2025.170784

A sub-5 ps jitter time-to-digital converter ASIC with back-gate delay tuning in 22 nm CMOS

Journal Article · Tue Jul 08 20:00:00 EDT 2025 · Nuclear Instruments and Methods in Physics Research. Section A, Accelerators, Spectrometers, Detectors and Associated Equipment

DOI:https://doi.org/10.1016/j.nima.2025.170784· OSTI ID:2570339

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Fermi National Accelerator Laboratory (FNAL), Batavia, IL (United States)
Fermi National Accelerator Laboratory (FNAL), Batavia, IL (United States); California Institute of Technology (CalTech), Pasadena, CA (United States)

We present the design of a Time-to-Digital Converter (TDC) ASIC together with performance characterization results at cryogenic temperature (6-8 K), and at room temperature using emulated Low-Gain Avalanche Detector (LGAD) signals. The TDC design uses a two-step architecture with a ring-oscillator based counter and a Vernier delay line fine TDC. The TDC is implemented in an FD-SOI process, and back-gate tuning is used not only to correct threshold variation due to cryogenic operation, but also as a novel way to tune TDC delay elements with very little overhead. Using this technique, we demonstrate a design with very low power (0.5 mW) and area (0.003 mm²). We present test results using the Fermilab Constant Fraction Discriminator (FCFD) ASIC to produce discriminated signals from an internal charge injection mechanism that mimics the waveform and signal amplitude of minimum ionizing particles impinging on LGAD sensors. We characterize the time precision of the full system and verify that the TDC ASIC contributes a negligible amount to the total system time precision, fully consistent with the expected jitter contribution of less than 5 ps. In conclusion, the results presented here demonstrate the utility of our TDC for applications in physics and quantum communications.

View Accepted Manuscript (DOE)

Research Organization:: Fermi National Accelerator Laboratory (FNAL), Batavia, IL (United States); California Institute of Technology (CalTech), Pasadena, CA (United States)

Sponsoring Organization:: USDOE Office of Science (SC), Basic Energy Sciences (BES). Scientific User Facilities (SUF); USDOE Office of Science (SC), High Energy Physics (HEP)

Grant/Contract Number:: 89243024CSC000002; SC0011925

OSTI ID:: 2570339

Report Number(s):: FERMILAB-PUB--25-0014-ETD; oai:inspirehep.net:2938307

Journal Information:: Nuclear Instruments and Methods in Physics Research. Section A, Accelerators, Spectrometers, Detectors and Associated Equipment, Journal Name: Nuclear Instruments and Methods in Physics Research. Section A, Accelerators, Spectrometers, Detectors and Associated Equipment Vol. 1080; ISSN 0168-9002

Publisher:: ElsevierCopyright Statement

Country of Publication:: United States

Language:: English

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A sub-5 ps jitter time-to-digital converter ASIC with back-gate delay tuning in 22 nm CMOS

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