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First test results of the trans-impedance amplifier stage of the ultra-fast HPSoC ASIC

Journal Article · · Journal of Instrumentation
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Abstract

We present the first results from the HPSoC ASIC designed for readout of Ultra-fast Silicon Detectors. The 4-channel ASIC manufactured in 65 nm CMOS by TSMC has been optimized for 50 μm thick AC-LGAD. The evaluation of the analog front end with β-particles impinging on 3 × 3 AC-LGAD arrays (500 μm pitch, 200 × 200 μm2metal) confirms a fast output rise time of 600 ps and good timing performance with a jitter of 45 ps. Further calibration experiments and TCT laser studies indicate some gain limitations that are being investigated and are driving the design of the second-generation pre-amplification stages to reach a jitter of 15 ps.

Research Organization:
Univ. of California, Santa Cruz, CA (United States); Nalu Scientific, LLC, Honolulu, HI (United States)
Sponsoring Organization:
USDOE Office of Science (SC)
DOE Contract Number:
SC0010107; SC0021755
OSTI ID:
2420008
Journal Information:
Journal of Instrumentation, Journal Name: Journal of Instrumentation Journal Issue: 02 Vol. 18; ISSN 1748-0221
Publisher:
Institute of Physics (IOP)
Country of Publication:
United States
Language:
English

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Instruments & Instrumentation